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                                          My PIC12F683 Development Board
Office Map Circuit diagram for each experiment may not be available separately because they are conducted with PIC12F683 development board that I made. So, the readers should first see the schematic of my development board.
Showing posts with label ISR. Show all posts
Showing posts with label ISR. Show all posts

Saturday, June 26, 2010

Experiment No. 4: External Interrupt

PIC12F683 has got one external interrupt pin (GP2, pin 5) which is edge-triggered:
  • rising edge if INTEDG bit in OPTION register is SET,or 
  • falling edge if INTEDG bit in OPTION register is CLEAR
In this experiment we are going to simulate an external interrupt event by a tact switch which when pressed gives a falling edge (5->0V) to external interrupt pin. When a valid edge appears on GP2/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing INTE control bit (INTCON<4>). While exiting from the Interrupt Service Routine, INTF flag must be cleared to re-enable the interrupt again. ANSEL and CMCON0 must be initialized to configure GPIO as digital I/Os.

On the arrival of an interrupt, the new value of counter will increase by 1 and is displayed as no. of interrupts serviced. 

Experimental Setup:
External interrupt will be simulated by a tact switch on the board. So connect SW1 to GP2 with a jumper wire. For display purpose we will again use a hyperterminal window on a PC.


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